ECP5 SerDes¶

Lattice Semiconductor ECP5/ECP5-5G SerDes Interfaces

class bakeneko.interface.phy.serdes.vendor.lattice.ecp5.DCU(*, dcu: DCUNumber, channel: Channel, link_speed: Literal[LinkSpeed.LS2_5, LinkSpeed.LS5_0], refclk: Signal, tx0_p: Signal | None = None, tx0_n: Signal | None = None, rx0_p: Signal | None = None, rx0_n: Signal | None = None, tx1_p: Signal | None = None, tx1_n: Signal | None = None, rx1_p: Signal | None = None, rx1_n: Signal | None = None, bitclk_from_next_dual: bool = False) → None¶

Lattice Semiconductor ECP5/ECP5-5G devices have a concept called a Dual-Channel Unit (DCU), it represents an encapsulation of 2 SerDes channels.

Each ECP5/ECP5-5G device has 2 DCUs on the larger 45k an 85k variants, and a single DCU on the smaller 25k variants with no DCUs the non-UM devices.

The overall structure of a DCU looks like this:

╭───────────╮
│    DCU    │
├─────┬─────┤
│ CH0 │ CH1 │
╰─────┴─────╯

Within each DCU, there is also an EXTREF block, which deals with internal reference clock generation from the DCU, as well as an auxiliary control channel.

A more detailed block diagram of a DCU would be as follows:

╭───────────────────────────────╮
│              DCU              │
│ ╭─────────╮ ╭─────────╮ ╭───╮ │
│ │         │ │         │ │ A │ │
│ │   CH0   │ │   CH1   │ │ U │ │
│ │         │ │         │ │ X │ │
│ ├─────────┤ ├─────────┤ ╰───╯ │
│ │         │ │         │ ╭───╮ │
│ │   PCS   │ │   PCS   │ │ E │ │
│ │         │ │         │ │ X │ │
│ ├─────────┤ ├─────────┤ │ T │ │
│ │ SERDES0 │ │ SERDES1 │ │ R │ │
│ ├────┬────┤ ├────┬────┤ │ E │ │
│ │ RX │ TX │ │ RX │ TX │ │ F │ │
│ ╰────┴────╯ ╰────┴────╯ ╰───╯ │
╰───────────────────────────────╯

For more details on the ECP5 DCUs see the Lattice Technical Note FPGA-TN-02206.

Note

Many of the DCU and channel properties are set at elaboration time for the synthesis and place-and-route tools, however, many, if not most of them are able to be modified via the SerDes Client Interface (SCI) for the DCU.

Parameters:

dcu (DCUNumber) – The specific DCU on the device to use.
channel (Channel) – The specific channel or channels to use for the given DCU.
link_speed (LinkSpeed) – The link speed for the DCUs channels.
refclk (Signal) – The input reference clock for this DCU
tx0_p (Signal | None) – The positive side of the channel 0 transmitter pair (default: None)
tx0_n (Signal | None) – The negative side of the channel 0 transmitter pair (default: None)
rx0_p (Signal | None) – The positive side of the channel 0 receiver pair (default: None)
rx0_n (Signal | None) – The negative side of the channel 0 receiver pair (default: None)
tx1_p (Signal | None) – The positive side of the channel 0 transmitter pair (default: None)
tx1_n (Signal | None) – The negative side of the channel 0 transmitter pair (default: None)
rx1_p (Signal | None) – The positive side of the channel 0 receiver pair (default: None)
rx1_n (Signal | None) – The negative side of the channel 0 receiver pair (default: None)
bitclk_from_next_dual (bool) –
Route the TX bitclock from the AUX channel of the DCU that is next to us.

e.g. If we are DCU0, then the TX bitclock will come from the AUX channel of DCU1. (default: False)

Attributes:

dcu_num (DCUNumber) – The DCU on the device this module is configured for
chan (Channel) – The DCU channel(s) this module is configured for
sci (DCUInterface) – The SerDes Client Interface for this DCU.

elaborate(platform: Platform | None) → Module¶

Return type:: Module

Todo

Document Me

class bakeneko.interface.phy.serdes.vendor.lattice.ecp5.ECP5SerDesPIPE → None¶

elaborate(platform: Platform | None) → Module¶

Return type:: Module

Todo

Document Me

class bakeneko.interface.phy.serdes.vendor.lattice.ecp5.SCI → None¶

Simple interface to interact with the ECP5/ECP5G’s SCI of a single DCU.

Attributes:

dcu_sel (Signal) – Target DCU
ch_sel (Signal) – Target DCU Channel
re (Signal) – Read-enable
we (Signal) – Write-enable
done (Signal) – Transaction done
addr (Signal) – 6-bit SCI Register address
data_w (Signal) – 8-bit write data
data_r (Signal) – 8-bit read data
interrupt (Signal) – The SCI interrupt signals

elaborate(platform: Platform | None) → Module¶

Return type:: Module

Todo

Document Me

class bakeneko.interface.phy.serdes.vendor.lattice.ecp5.CHRegister(value)¶

Channel Control/Status registers as defined in Lattice Technical Note FPGA-TN-02206.

CH_00 = 0¶

## PCS Control Register 1

Bits	Name \| Description		Type	Default
0	uc_mode	1 - Selects User Configured Mode 0 - Selects other Mode (PCIe, RapidIO, etc. )	R/W	`0b0`
1	Reserved
2	pcie_mode	1 - PCIe Mode 0 - Selects other mode (RapidIO, 10GbE, 1GbE)	R/W	`0b0`
3	rio_mode	1 - Selects Rapid-IO Mode 0 - Selects other mode (10GbE, 1GbE)	R/W	`0b0`
4	wa_mode	1 - Bit-slip word alignment mode 0 - Barrel shift word alignment mode	R/W	`0b0`
7:5	Reserved		R/W	`0b0`

CH_01 = 1¶

## PCS Control Register 2

Bits	Name	Description	Type	Default
0	invert_rx	1 - Invert received data 0 - Do not invert received data	R/W	`0b0`
1	invert_tx	1 - Invert transmitted data 0 - Do not invert transmitted data	R/W	`0b0`
2	Internal
3	Reserved
4	ge_an_enable	1 - Enable GigE Auto-Negotiation 0 - Disable GigE Auto-Negotiation	R/W	`0b0`
5	Internal
6	Internal
7	enable_cg_align	Only valid when in uc_mode 1 - Enable continuous comma alignment 0 - Disable continuous comma alignment	R/W	`0b0`

CH_02 = 2¶

## PCS Control Register 3

Bits	Name	Description	Type	Default
0	tx_ch	1 - Transmit PCS inputs are sourced from test characterization ports. The test characterization mode should be enabled.	R/W	`0b0`
1:0	Reserved
2	tx_gear_mode	1 - Enable 2:1 gearing for transmit path on selected channels. 0 - Disable 2:1 gearing for transmit path on selected channels (no gearing)	R/W	`0b0`
3	rx_gear_mode	1 - Enable 2:1 gearing for receive path on selected channels. 0 - Disable 2:1 gearing for receive path on selected channels (no gearing)	R/W	`0b0`
5:4	pcs_det_time_sel[1:0]	PCS Connection detection time 11 - 16µs 10 - 04µs 01 - 02µs 00 - 08µs	R/W	`0b0`
6	pcie_ei_en	1 - PCI Express Electrical Idle 0 - Normal Operation	R/W	`0b0`
7	pfifo_clr	1 - Clears PFIFO if DCU bit `pfifo_clr_sel` is set to `1`. This signal is or-ed with interface signal `pfifo_clr`. 0 - Normal Operation	R/W	`0b0`

CH_03 = 3¶

## PCS Control Register 4

Bits	Name	Description	Type	Default
0	fb_loopback	1 - Enable loopback in the PCS just before the FPGA bridge from RX to TX. 0 - Normal data operation.	R/W	`0b0`
1	tx_gear_bypass	1 - Bypass PCS Transmission Gearbox 0 - Normal Operation	R/W	`0b0`
2	Internal
3	enc_bypass	1 - Bypass 8b10b encoder 0 - Normal Operation	R/W	`0b0`
4	Internal
5	sb_pfifo_lp	1 - Enabled parallel loopback from rx to tx through the parallel FIFO 0 - Normal data operation	R/W	`0b0`
6	sb_bypass	1 - Invert TX data after SerDes Bridge 0 - Dont invert TX data after SerDes bridge Note: Loopback data is also inverted	R/W	`0b0`
7	Reserved

CH_04 = 4¶

## PCS Control Register 5

Bits	Name	Description	Type	Default
0	sb_loopback	1 - Enable loopback in the PCS from TX to RX in the SerDes bridge. 0 - Normal data operation	R/W	`0b0`
1	rx_sb_bypass	1 - Invert RX data after SerDes bridge 0 - Normal operation	R/W	`0b0`
2	wa_bypass	1 - Bypass word alignment 0 - Dont invert RX data after SerDes bridge Note: Loopack data is inverted	R/W	`0b0`
3	dec_bypass	1 - Bypass 8b10b decoder 0 - Normal operation	R/W	`0b0`
4	ctc_bypass	1 - Bypass clock tolerance compensation 0 - Normal operation	R/W	`0b0`
5	rx_gear_bypass	1 - Bypass PCS RX Gearbox 0 - Normal operation	R/W	`0b0`
6	signal_detect	1 - Force enable the RX link state machine 0 - RX link state machine is enabled depending on the setting of `ffc_signal_detect`	R/W	`0b0`
7	lsm_disable	1 - Disable RX link state machine 0 - Enable RX link state machine	R/W	`0b0`

CH_05 = 5¶

## PCS Control Register 6

Bits	Name	Description	Type	Default
3:0	Reserved
4	match_2_enable	1 - Enable two character skip matching (using match 4,3)	R/W	`0b1`
5	match_4_enable	1 - Enable four character skip matching (using 4,3,2,1)	R/W	`0b0`
7:6	min_ipg_cng[1:0]	Minimum IPG to enforce	R/W	`0b11`

NOTE: If neither match bit is enabled, signal character skip matching is performed using match 4

CH_06 = 6¶

## PCS Control Register 7 - CC Match 1 LO

Bits	Name	Description	Type	Default
7:0	cc_match_1[7:0]	Lower pattern of bits for user-defined clock compensator skip pattern #1	R/W	`0x00`

CH_07 = 7¶

## PCS Control Register 8 - CC Match 2 LO

Bits	Name	Description	Type	Default
7:0	cc_match_2[7:0]	Lower pattern of bits for user-defined clock compensator skip pattern #2	R/W	`0x00`

CH_08 = 8¶

## PCS Control Register 9 - CC Match 3 LO

Bits	Name	Description	Type	Default
7:0	cc_match_3[7:0]	Lower pattern of bits for user-defined clock compensator skip pattern #3	R/W	`0x00`

CH_09 = 9¶

## PCS Control Register 10 - CC Match 4 LO

Bits	Name	Description	Type	Default
7:0	cc_match_4[7:0]	Lower pattern of bits for user-defined clock compensator skip pattern #4	R/W	`0x00`

CH_0A = 10¶

## PCS Control Register 11 - CC Match HI

Bits	Name	Description	Type	Default
1:0	cc_match_1[9:8]	Upper pattern bits for user defined clock compensator skip pattern #1 Bit 9 - Disparity Error Bit 8 - K Control	R/W	`0b00`
2:3	cc_match_2[9:8]	Upper pattern bits for user defined clock compensator skip pattern #2 Bit 9 - Disparity Error Bit 8 - K Control	R/W	`0b00`
4:5	cc_match_3[9:8]	Upper pattern bits for user defined clock compensator skip pattern #3 Bit 9 - Disparity Error Bit 8 - K Control	R/W	`0b01`
7:6	cc_match_4[9:8]	Upper pattern bits for user defined clock compensator skip pattern #4 Bit 9 - Disparity Error Bit 8 - K Control	R/W	`0b01`

CH_0B = 11¶

## PCS Control Register 12 - UDF Comma Mask LO

Bits	Name	Description	Type	Default
7:0	udf_comma_mask[7:0]	Lower bits of user-defined comma mask	R/W	`0xFF`

CH_0C = 12¶

## PCS Control Register 13 - UDF Comma A LO

Bits	Name	Description	Type	Default
7:0	udf_comma_a[7:0]	Lower bits of user-defined comma character `a`	R/W	`0x83`

CH_0D = 13¶

## PCS Control Register 14 - UDF Comma B LO

Bits	Name	Description	Type	Default
7:0	udf_comma_b[7:0]	Lower bits of user-defined comma character `b`	R/W	`0x7C`

CH_0E = 14¶

## PCS Control Register 15 - UDF Comma HI

Bits	Name	Description	Type	Default
1:0	Reserved
2:3	udf_comma_mask[9:8]	Upper pattern bits for user defined comma mask Bit 9 - Disparity Error Bit 8 - K Control	R/W	`0b11`
4:5	udf_comma_a[9:8]	Upper pattern bits for user defined comma character `a` Bit 9 - Disparity Error Bit 8 - K Control	R/W	`0b01`
7:6	udf_comma_b[9:8]	Upper pattern bits for user defined comma character `b` Bit 9 - Disparity Error Bit 8 - K Control	R/W	`0b10`

CH_0F = 15¶

## PCS Control Register 16

Bits	Name	Description	Type	Default
0	fb_tx_fifo_error_int_ctl	1 - Enable interrupt on empty/full condition in the TX FIFO on the FPGA bridge	R/W	`0b0`
1	fb_rx_fifo_error_int_ctl	1 - Enable interrupt on empty/full condition in the RX FIFO on the FPGA bridge	R/W	`0b0`
2	cc_overrun_int_ctl	1 - Enable interrupt for cc_overrun 0 - Disable interrupt for cc_overrun	R/W	`0b0`
3	cc_underrun_int_ctl	1 - Enable interrupt for cc_underrun 0 - Disable interrupt for cc_underrun	R/W	`0b0`
7:4	Reserved

CH_10 = 16¶

## SerDes Control Register 1

Bits	Name	Description	Type	Default
0	tpwdnb	1 - Power down transmit channel 0 - Power up transmit channel	R/W	`0b0`
1	rate_mode_tx	1 - Full rate selection for transmit 0 - Half rate selection for transmit	R/W	`0b0`
2	tx_div11_sel	1 - Full rate selection for transmit 0 - Divide by 11 selection for transmit	R/W	`0b0`
3	ldr_core2tx_sel	1 - Select low-speed serial data from FPGA Core	R/W	`0b0`
4	tdrv_pre_en	1 - TX Driver pre-emphasis enable 0 - TX Driver pre-emphasis disable	R/W	`0b0`
5	tdrv_post_en	1 - TX Driver post-emphasis enable 0 - TX Driver post-emphasis disable	R/W	`0b0`
6	tx_pre_sign	1 - TX pre-emphasis not inverted 0 - TX pre-emphasis inverted	R/W	`0b0`
7	tx_post_sign	1 - TX post-emphasis not inverted 0 - TX post-emphasis inverted	R/W	`0b0`

CH_11 = 17¶

## SerDes Control Register 2

Bits	Name	Description	Type	Default
4:0	rterm_tx[4:0]	TX Resistor termination select. Disabled in PCIe Mode. 00000 - 5kΩ 00001 - 80Ω 00100 - 75Ω 00110 - 70Ω 01011 - 60Ω 10011 - 50Ω 11001 - 46Ω NOTE: Other values reserved	R/W	`0b0000`
5:6	tx_cm_sel[1:0]	Select output common mode voltage. 00 - Power Down 01 - 0.60V 10 - 0.55V 11 - 0.50V	R/W	`0b00`
7	Internal

CH_12 = 18¶

## SerDes Control Register 3

Bits	Name	Description	Type	Default
1:0	tdrv_slice0_sel[1:0]	TX Drive slice enable for slice 0 00 - Power Down 01 - Select Main Data 10 - Select Pre Data 11 - Select Post Data	R/W	`0b00`
3:2	tdrv_slice1_sel[1:0]	TX Drive slice enable for slice 1 00 - Power Down 01 - Select Main Data 10 - Select Pre Data 11 - Select Post Data	R/W	`0b00`
5:4	tdrv_slice2_sel[1:0]	TX Drive slice enable for slice 2 00 - Power Down 01 - Select Main Data 10 - Select Pre Data 11 - Select Post Data	R/W	`0b00`
7:6	tdrv_slice3_sel[1:0]	TX Drive slice enable for slice 3 00 - Power Down 01 - Select Main Data 10 - Select Pre Data 11 - Select Post Data	R/W	`0b00`

CH_13 = 19¶

## SerDes Control Register 4

Bits	Name	Description	Type	Default
3:0	Internal
5:4	tdrv_slice3_cur[1:0]	Controls the output current for slice 3. Every 100µA increases the output amplitude by 100mV. 00 - 0800µA 01 - 1600µA 10 - 2400µA 11 - 3200µA	R/W	`0b00`
7:6	tdrv_slice4_cur[1:0]	Controls the output current for slice 4. Every 100µA increases the output amplitude by 100mV. 00 - 0800µA 01 - 1600µA 10 - 2400µA 11 - 3200µA	R/W	`0b00`

CH_14 = 20¶

## SerDes Control Register 5

Bits	Name	Description	Type	Default
2:0	tdrv_slice0_cur[2:0]	Controls the output current for slice 0. Every 100µA increases the output amplitude by 100mV. 000 - 100µA 001 - 200µA 010 - 300µA 011 - 400µA 100 - 500µA 101 - 600µA 110 - 700µA 111 - 800µA	R/W	`0b00`
5:3	tdrv_slice1_cur[2:0]	Controls the output current for slice 1. Every 100µA increases the output amplitude by 100mV. 000 - 100µA 001 - 200µA 010 - 300µA 011 - 400µA 100 - 500µA 101 - 600µA 110 - 700µA 111 - 800µA	R/W	`0b00`
7:6	tdrv_slice2_cur[1:0]	Controls the output current for slice 2. Every 100µA increases the output amplitude by 100mV. 00 - 0800µA 01 - 1600µA 10 - 2400µA 11 - 3200µA	R/W	`0b00`

CH_15 = 21¶

## SerDes Control Register 6

Bits	Name	Description	Type	Default
3:0	lb_ctl[3:0]	Serial loopback control bitfield. Bit 3 - slb_r2t_dat_en Serial RX to TX LB enable, CDR DAT Bit 2 - slb_r2t_ck_en Serial RX to TX LB enable, CDR CLK Bit 1 - slb_eq2t_en Serial loopback from equalizer to drv Bit 0 - slb_t2r_en Serial TX to RX loopback enable	R/W	`0b0000`
5:4	tdrv_dat_sel[1:0]	Driver output selection 00 - Data from serializer is muxed to driver 01 - Data rate clock from serializer is muxed to driver 10 - Serial RX to TX LB (data) if slb_r2t_dat_en is `1` 10 - Serial RX to TX LB (clock) if slb_r2t_ck_en is `1` 11 - Serial LB from equalizer if slb_eq2t_en is `1`	R/W	`0b00`
7:6	tdrv_slice5_cur[1:0]	Controls the output current for slice 2. Every 100µA increases the output amplitude by 100mV. 00 - 0800µA 01 - 1600µA 10 - 2400µA 11 - 3200µA	R/W	`0b00`

CH_16 = 22¶

## SerDes Control Register 7

Bits	Name	Description	Type	Default
0	rpwdnb	1 - Power down receiver channel 0 - Power up receiver channel	R/W	`0b0`
1	rate_mode_rx	1 - Full rate selection for receiver 0 - Half rate selection for receiver	R/W	`0b0`
2	rx_div11_sel	1 - Full rate selection for receiver 0 - Divide by 11 selection for receiver	R/W	`0b0`
3	ldr_rx2core_sel	Enables boundary scan input path for routing the high-speed RX inputs to a lower speed SerDes in the FPGA fabric	R/W	`0b0`
4	rx_refck_sel	RX CDR Reference Clock Select 1 - ck_core_rx 0 - rx_refck_local	R/W	`0b0`
5	rcv_dcc_en	1 - Receiver DC coupling 0 - Receiver AC coupling	R/W	`0b0`
7:6	rxterm_cm[1:0]	Command mode volate for RX input term 00 - RX Input Supply 01 - Floating (AC Ground) 10 - GND 11 - RX Input Supply	R/W	`0b00`

CH_17 = 23¶

## SerDes Control Register 8

Bits	Name	Description	Type	Default
4:0	rterm_rx[4:0]	RX Resistor termination select. 00000 - 5.0kΩ 00001 - 80.0Ω 00010 - 78.6Ω 00011 - 76.7Ω 00100 - 75.0Ω 00101 - 73.4Ω 00110 - 70.5Ω 00111 - 68.0Ω 01001 - 63.7Ω 01010 - 62.0Ω 01011 - 60.0Ω 01100 - 58.2Ω 01101 - 56.6Ω 01110 - 55.2Ω 01111 - 54.0Ω 10000 - 52.8Ω 10001 - 51.8Ω 10010 - 50.9Ω 10011 - 50.0Ω 10100 - 49.2Ω 10101 - 48.5Ω 10110 - 47.8Ω 10111 - 47.2Ω 11000 - 46.6Ω 11001 - 46.0Ω NOTE: Other values reserved	R/W	`0b0000`
5	Reserved
7:6	rcin_cm[1:0]	Common mode voltage for equalizer input in AC-coupling 00 - 0.70V 01 - 0.65V 10 - 0.75V 11 - CMFB	R/W	`0b00`

CH_18 = 24¶

## SerDes Control Register 9

Bits	Name	Description	Type	Default
5:0	Reserved
6	fc2dco_floop	Force DCO to lock to the frequency loop	R/W	`0b0`
7	fc2dco_dloop	Force DCO to lock to the data loop	R/W	`0b0`

CH_19 = 25¶

## SerDes Control Register 10

Bits	Name	Description	Type	Default
0	req_en	1 - Enable receiver equalization 0 - Disable receiver equalization	R/W	`0b0`
4:1	rx_rate_sel[3:0]	Equalizer pole position selection	R/W	`0x0`
6:5	req_lvl_set[1:0]	Equalization level setting 00 - 06dB 01 - 09dB 10 - 12dB 11 - Unused	R/W	`0b00`
7	Reserved

CH_1A = 26¶

## SerDes Control Register 11

Bits	Name	Description	Type	Default
2:0	rx_dco_ck_div[2:0]	VCO Output frequency selector 000 - Divided by 1 001 - Divided by 1 010 - Divided by 2 011 - Divided by 2 100 - Divided by 4 101 - Divided by 8 110 - Divided by 16 111 - Divided by 32	R/W	`0b000`
3	pden_sel	1 - Disable phase detector if los is `0` 0 - Don’t disable phase detector if los is `0`	R/W	`0b0`
4	dco_facq_rst	Trigger DCO frequency acquistion reset when needed	R/W	`0b0`
5	dco_calib_rst	Trigger DCO calibration reset when needed	R/W	`0b0`
6	en_recalib	1 - Enable recalibration 0 - Disable recalibaration	R/W	`0b0`
7	band_calib_mode	1 - Enable 0 - Disable	R/W	`0b0`

CH_1B = 27¶

## SerDes Control Register 12

Bits	Name	Description	Type	Default
2:0	rx_los_lvl[2:0]	Sets the peak-to-peak threashold voltage for LoS detection	R/W	`0b000`
4:3	rx_los_ceq[1:0]	Sets the equalization value at the input stage of the LoS detector.	R/W	`0b00`
5	rx_los_hyst_en	1 - Enable hysteresis for LoS detection threshold 0 - Disalbe hysteresis for LoS detection threshold	R/W	`0b0`
6	rx_los_en	1 - Enable loss-of-signal (LoS) detector 0 - Disable loss-of-signal (LoS) detector	R/W	`0b0`
7	rlos_sel	1 - Enable LoS detetion before CDR phase detector 0 - Disable LoS detetion before CDR phase detector	R/W	`0b0`

CH_1E = 30¶

## SerDes Interrupt Control Register 1

Bits	Name	Description	Type	Default
0	~rlol_int_ctl	Enable interrupt when receiver is locked	R/W	`0b0`
1	rlol_int_ctl	Enable interrupt when reciever loses lock	R/W	`0b0`
2	Reserved
3	Reserved
4	~rlos_int_ctl	Enable interrupt for RX LoS when input level meets or is above `rlos_set` low threashold.	R/W	`0b0`
5	rlos_int_ctl	Enable interrupt for RX LoS when input level fall below `rlos_set` low threashold.	R/W	`0b0`
6	pcie_det_done_int_ctl	Enable interrupt for detection of a far end PCIe receiver.	R/W	`0b0`
7	Reserved

CH_1F = 31¶

## Reset and Clock Control Register 1

Bits	Name	Description	Type	Default
0	sel_sd_rx_clk	1 - FPGA Bridge write clock and elastic buffer read clock driven by SerDes recovered clock. 0 - FPGA Bridge write clock and elastic buffer read clock driven by `ff_ebrd_clk`.	R/W	`0b0`
1	ff_rx_h_clk_en	Enable `fx_rx_h_clk`	R/W	`0b0`
2	ff_rx_f_clk_dis	Disable `ff_rx_f_clk`	R/W	`0b0`
3	ff_tx_h_clk_en	Enable `ff_tx_h_clk`	R/W	`0b0`
4	ff_tx_f_clk_dis	Disable `ff_tx_f_clk`	R/W	`0b0`
5	lane_tx_rst	Reset transmit logic	R/W	`0b0`
6	lane_rx_rst	Reset receive logic	R/W	`0b0`
7	rrst	Reset receiver	R/W	`0b0`

CH_30 = 48¶

## PCS Status Register 1

Bits	Name	Description	Type	Interrupt
0	fb_tx_fifo_error	1 - FPGA Bridge TX FIFO overrun 0 - FPGA Bridge TX FIFO not overrun	RO	Yes
1	fb_rx_fifo_error	1 - FPGA Bridge RX FIFO overrun 0 - FPGA Bridge RX FIFO not overrun	RO	Yes
2	cc_overrun	1 - CC FIFO overrun 0 - CC FIFO not overrun	RO	Yes
3	cc_underrun	1 - CC FIFO underrun 0 - CC FIFO not underrun	RO	Yes
4	pfifo_error	1 - Parallel FIFO error 0 - No Parallel FIFO error	RO	Yes
7:5	Reserved		RO	Yes

CH_31 = 49¶

## PCS Status Register 2

Bits	Name	Description	Type	Interrupt
7:0	prbs_error_cnt[7:0]	Number of PRBS errors. Resets to `0` on read and sticks at `0xFF`.	RO CR	No

CH_32 = 50¶

## PCS Status Register 3

Bits	Name	Description	Type	Interrupt
3:0	wa_offset[3:0]	Word aligner offset	RO	No
7:4	Reserved

CH_33 = 51¶

## PCS Status Register 4

Bits	Name	Description	Type	Interrupt
0	fb_tx_fifo_error_int	1 - Interrupt generated on `fb_tx_fifo_error` 0 - Interrupt not generated on `fb_tx_fifo_error`	RO CR	Yes
1	fb_rx_fifo_error_int	1 - Interrupt generated on `fb_rx_fifo_error` 0 - Interrupt not generated on `fb_rx_fifo_error`	RO CR	Yes
2	cc_overrun_int	1 - Interrupt generated on `cc_overrun` 0 - Interrupt not generated on `cc_overrun`	RO CR	Yes
3	cc_underrun_int	1 - Interrupt generated on `cc_underrun` 0 - Interrupt not generated on `cc_underrun`	RO CR	Yes
7:4	Reserved

CH_34 = 52¶

## PCS Status Register 5

Bits	Name	Description	Type	Interrupt
0	cc_we_o	1 - Elsatic FIFO write enabled 0 - Elsatic FIFO write disabled	RO	No
1	cc_re_o	1 - Elastic FIFO read enabled 0 - Elastic FIFO read disabled	RO	No
3:2	Reserved
4	fb_txrst_o	1 - FPGA Bridge TX Normal Operation 0 - FPGA Bridge TX Reset	RO	No
5	fb_rxrst_o	1 - FPGA Bridge RX Normal Operation 0 - FPGA Bridge RX Reset	RO	No
6	ffs_ls_sync_status	1 - Link State Machine not Synced 0 - Link State Machine Synced	RO	No
7	Reserved

CH_36 = 54¶

## SerDes Status Register 1

Bits	Name	Description	Type	Interrupt
0	~rlol	If CDR has locked to data	RO	Yes
1	rlol	If CDR is not locked to data, but to refclock	RO	Yes
3:2	Reserved		RO CR	Yes
4	~rlos	If the input signal detected by the receiver is equal to or greater than the set threshold for LOW	RO CR	Yes
5	rlos	If the input signal detected by the receiver is below the set LOW threashold.	RO CR	Yes
6	pci_det_done	1 - Receiver detection process completed by TX 0 - Receiver detection process not completed by TX	RO CR	Yes
7	Reserved

CH_37 = 55¶

## SerDes Status Register 2

Bits	Name	Description	Type	Interrupt
0	pci_connect	1 - Receiver detected by transmitter (at transmitter device) 0 - Receiver not detected by transmitter (at transmitter device)	RO	No
3:1	Reserved
4	dco_facq_done	If DCO frequency acquisition done	RO	No
5	dco_facq_err	If DCO frequency acquisition is more than 300ppm	RO	No
6	dco_calib_done	If DCO calibration is completed	RO	No
7	dco_calib_err	If DCO calibration might be incorrect	RO	No

CH_3A = 58¶

## SerDes Status Register 5

Bits	Name	Description	Type	Interrupt
0	~rlol_int	Interrupt generated for `~rlol`	CO CR	Yes
1	rlol_int	Interrupt generated for `rlol`	CO CR	Yes
3:2	Reserved
4	~rlos_int	Interrupt generated for `~rlos`	CO CR	Yes
5	rlos_int	Interrupt generated for `rlos`	CO CR	Yes
6	pci_det_done_int	Interrupt generated for `pci_det_done`	CO CR	Yes
7	Reserved

class bakeneko.interface.phy.serdes.vendor.lattice.ecp5.DCURegister(value)¶

DCU Control/Status registers as defined in Lattice Technical Note FPGA-TN-02206.

DL_00 = 0¶

## PCS Control Register 1

Bits	Name	Description	Type	Default
3:0	Reserved		R/W	`0b0`
4	xge_mode	1 - Select 10GbE (Different XAUI LSM and 8b10b) 0 - Depends on Channel Mode selection	R/W
5	char_mode	1 - Enable SerDes characterization mode 0 - Disable SerDes characterization mode	R/W	`0b0`
6	force_int	1 - Force generation of an interrupt 0 - Normal operation	R/W	`0b0`
7	reg_sync_toggle	Trans - Reset TX Serializers to minimize lane skew Level - Normal operation	R/W	`0b0`

DL_02 = 2¶

## PCS Control Register 3

Bits	Name	Description	Type	Default
3:0	low_mark	Clock compensation FIFO low water mark, mean is 8	R/W	`0b0101`
7:4	high_mark	Clock compensation FIFO high water mark, mean is 8	R/W	`0b0101`

DL_03 = 3¶

## PCS Control Register 4

Bits	Name	Description	Type	Default
1:0	Reserved
2	pfifo_clr_sel	1 - pfifo_clr signal/channel bit clears FIFO 0 - pfifo_error signal clears FIFO	R/W	`0b0`
7:3	Reserved		R/W	`0b0`

DL_09 = 9¶

## PCS Interrupt Control Register 10

Bits	Name	Description	Type	Default
0	ls_sync_statusn_0_int_ctrl	1 - Enable interrupt for ls_sync_statusn_0 on OoS 0 - Disable interrupt for ls_sync_statusn_0 on OoS	R/W	`0b0`
1	ls_sync_statusn_1_int_ctrl	1 - Enable interrupt for ls_sync_statusn_1 on OoS 0 - Disable interrupt for ls_sync_statusn_1 on OoS	R/W	`0b0`
2:3	Reserved
4	ls_sync_status_0_int_ctrl	1 - Enable interrupt for ls_sync_status_0 on In Sync 0 - Disable interrupt for ls_sync_status_0 on In Sync	R/W	`0b0`
5	ls_sync_status_1_int_ctrl	1 - Enable interrupt for ls_sync_status_1 on In Sync 0 - Disable interrupt for ls_sync_status_1 on In Sync	R/W	`0b0`
6:7	Reserved

DL_0A = 10¶

## SerDes Control Register 1

Bits	Name	Description	Type	Default
0	refck_out_sel[0]	1 - rx_refck_local output enabled 0 - rx_refck_local output disabled	R/W	`0b00`
1	refck_out_sel[1]	1 - refck_to_core output enabled 0 - refck_to_core output disabled	R/W	`0b00`
2	Reserved
3	refck_rterm	1 - REFCLK Termination is 100Ω 0 - REFCLK Terminatino is high impedance	R/W	`0b0`
4	refck_dcbias_en	1 - Enable internal refclk DC bias 0 - Disable internal refclk DC bias	R/W	`0b0`
5	tx_refck_sel	1 - TxPLL is ck_core_tx 0 - TxPLL is rx_refck_local	R/W	`0b0`
6	Reserved		R/W	`0b0`
7	Internal

DL_0B = 11¶

## SerDes Control Register 2

Bits	Name	Description	Type	Default
1:0	refck_mode[1:0]	iff `refclk25x` is 0: 00 - Internal bitclock is 20x 01 - Internal bitclock is 10x 10 - Internal bitclock is 16x 11 - Internal bitclock is 8x iff `refclk25x` is 1: xx - Internal bitclock is 25x	R/W	`0b00`
2	refck_to_nd_en	1 - Enable REFCLK to neighbor DCU	R/W	`0b0`
3	refck_from_nd_sel[0]	1 - Select TX REFCLK from neighbor DCU	R/W	`0b0`
4	refck_from_nd_sel[1]	1 - Select RX REFCLK from neighbor DCU	R/W	`0b0`
5	Reserved
6	bus8bit_sel	1 - Select 8-bit bus width 0 - Select 10-bit bus width	R/W	`0b0`
7	refclk25x	1 - Internal bitclock is 25x (for 100MHz REFCLK only) 0 - Use `refck_mode`	R/W	`0b0`

DL_0C = 12¶

## SerDes Control Register 4

Bits	Name	Description	Type	Default
1:0	cdr_lol_set[1:0]	00 - ±1000ppm x2 (Lock) ±1500ppm x2 (Unlock) 01 - ±2000ppm (Lock) ±2500ppm (Unlock) 10 - ±4000ppm (Lock) ±7000ppm (Unlock) 11 - ±300ppm (Lock) ±450ppm (Unlock)	R/W	`0b00`
7:2	Reserved

DL_0D = 13¶

## SerDes Control Register 4

Bits	Name	Description	Type	Default
2:0	tx_vco_ck_div[2:0]	00x - Divide by 1 01x - Divide by 2 100 - Divide by 4 101 - Divide by 8 110 - Divide by 16 111 - Divide by 32	R/W	`0b000`
4:3	pll_lol_set[1:0]	00 - ±300ppm x2 (Lock) ±600ppm x2 (Unlock) 01 - ±300ppm (Lock) ±2000ppm (Unlock) 10 - ±1500ppm (Lock) ±2200ppm (Unlock) 11 - ±4000ppm (Lock) ±6000ppm (Unlock)	R/W	`0b00`
5	Reserved
7:6	Reserved

DL_0F = 15¶

## SerDes Interrupt Control Register 6

Bits	Name	Description	Type	Default
5:0	Reserved
6	~PLOL_INT_CTRL	1 - Interrupt enabled for lock obtained on PLOL 0 - Interrupt disabled for lock obtained on PLOL	R/W	`0b0`
7	PLOL_INT_CTRL	1 - Interrupt enabled for loss of lock on PLOL 0 - Interrupt disabled for loss of lock on PLOL	R/W	`0b0`

DL_10 = 16¶

## Reset and Clock Control Register 1

Bits	Name	Description	Type	Default
0	trst	1 - Reset TxPLL Loss of Lock	R/W	`0b0`
1	dcu_rst	1 - Assert DCU Reset	R/W	`0b0`
2	macro_rst	1 - Assert macro Reset	R/W	`0b0`
3	macro_pdb	0 - Assert power down	R/W	`0b1`
4	refclk_pdnb	0 - Power Down REFCLK 1 - Power Up REFCLK	R/W	`0b0`
5	txpll_pdnb	0 - Power Down TX PLL 1 - Power Up TX PLL	R/W	`0b0`
6	Reserved
7	Reserved

DL_20 = 32¶

## PCS Status Register 1

Bits	Name	Description	Type	Interrupt
1:0	int_cha_out[1:0]	Per Channel Interrupt Status	RO	No
3:2	Reserved
4	int_dua_out	Per DCU Interrupt Status	RO	No
5	Spare	Delayed global rstn from tri_ion	RO	No
7:6	Reserved

DL_21 = 33¶

## PCS Packet Interrupt Status Register 2

Bits	Name	Description	Type	Interrupt
0	ls_sync_statusn_0	1 - Alarm generated on ls_sync_status_0 when OoS 0 - Alarm not generated on ls_sync_status_0 when OoS	RO	Yes
1	ls_sync_statusn_1	1 - Alarm generated on ls_sync_status_1 when OoS 0 - Alarm not generated on ls_sync_status_1 when OoS	RO	Yes
3:2	Reserved
4	ls_sync_status_0	1 - Alarm generated on ls_sync_status_0 when In Sync 0 - Alarm not generated on ls_sync_status_0 when In Sync	RO	Yes
5	ls_sync_status_1	1 - Alarm generated on ls_sync_status_1 when In Sync 0 - Alarm not generated on ls_sync_status_1 when In Sync	RO	Yes
6:7	Reserved

DL_22 = 34¶

## PCS Packet Interrupt Status Register 3

Bits	Name	Description	Type	Interrupt
0	ls_sync_statusn_0_int	1 - Interrupt generated on ls_sync_status_0 when OoS 0 - Interrupt not generated on ls_sync_status_0 when OoS	RO CR	Yes
1	ls_sync_statusn_1_int	1 - Interrupt generated on ls_sync_status_1 when OoS 0 - Interrupt not generated on ls_sync_status_1 when OoS	RO CR	Yes
3:2	Reserved
4	ls_sync_status_0_int	1 - Interrupt generated on ls_sync_status_0 when In Sync 0 - Interrupt not generated on ls_sync_status_0 when In Sync	RO CR	Yes
5	ls_sync_status_1_int	1 - Interrupt generated on ls_sync_status_1 when In Sync 0 - Interrupt not generated on ls_sync_status_1 when In Sync	RO CR	Yes
7:6	Reserved

DL_25 = 37¶

## SerDes Interrupt Status Register 1

Bits	Name	Description	Type	Interrupt
5:0	Reserved
6	~plol_sts	1 - PLL lock obtained	RO	Yes
7	plol_sts	1 - PLL Loss of Lock	RO	Yes

DL_26 = 38¶

## SerDes Interrupt Status Register 2

Bits	Name	Description	Type	Interrupt
5:0	Reserved
6	~plol_int	1 - Interrupt generated on ~PLOL 0 - Interrupt not generated on ~PLOL	RO CR	Yes
7	plol_int	1 - Interrupt generated on PLOL 0 - Interrupt not generated on PLOL	RO CR	Yes