DCU

Lattice Semiconductor ECP5/ECP5-5G Dual-Channel Unit (DCU) Interface.

class bakeneko.interface.phy.serdes.vendor.lattice.ecp5.dcu.DCU → None

Lattice Semiconductor ECP5/ECP5-5G devices have a concept called a Dual-Channel Unit (DCU), it represents an encapsulation of 2 SerDes channels.

Each ECP5/ECP5-5G device has 2 DCUs on the larger 45k an 85k variants, and a single DCU on the smaller 25k variants with no DCUs the non-UM devices.

The overall structure of a DCU looks like this:

╭───────────╮
│    DCU    │
├─────┬─────┤
│ CH0 │ CH1 │
╰─────┴─────╯

Within each DCU, there is also an EXTREF block, which deals with internal reference clock generation from the DCU, as well as an auxiliary control channel.

A more detailed block diagram of a DCU would be as follows:

╭───────────────────────────────╮
│              DCU              │
│ ╭─────────╮ ╭─────────╮ ╭───╮ │
│ │         │ │         │ │ A │ │
│ │   CH0   │ │   CH1   │ │ U │ │
│ │         │ │         │ │ X │ │
│ ├─────────┤ ├─────────┤ ╰───╯ │
│ │         │ │         │ ╭───╮ │
│ │   PCS   │ │   PCS   │ │ E │ │
│ │         │ │         │ │ X │ │
│ ├─────────┤ ├─────────┤ │ T │ │
│ │ SERDES0 │ │ SERDES1 │ │ R │ │
│ ├────┬────┤ ├────┬────┤ │ E │ │
│ │ RX │ TX │ │ RX │ TX │ │ F │ │
│ ╰────┴────╯ ╰────┴────╯ ╰───╯ │
╰───────────────────────────────╯

For more details on the ECP5 DCUs see the Lattice Technical Note FPGA-TN-02206.